Driving and Layout Design for Fast Switching Super-Junction MOSFETs

Power MOSFET technology has been developed towards higher cell density for lower on-resistance. There are, however, silicon limits for significant reduction in the onresistance with the conventional planar MOSFET technology because of its exponential increase in onresistance according to the increase of blocking capability. One of efforts to overcome the silicon limit is superjunction technology in high-voltage power MOSFETs. The super-junction technology can dramatically reduce both onresistance and parasitic capacitances, which usually are in trade-off. With smaller parasitic capacitances, the superjunction MOSFETs have extremely fast switching characteristics and reduced switching losses. Naturally, this switching behavior occurs with greater dv/dt and di/dt that affect switching performance via parasitic components in devices and printed circuit board. It is also related to EMI performance of the system. Therefore, an optimized design is very important to operate high-speed MOSFETs. The purpose of this application note is to discuss driving methods and layout requirements in relation to switching performance of fast switching MOSFETs.